This invention relates to an instruction prefetching device for use in a data or information processing system.
An instruction prefetching device is for use in prefetching an instruction sequence. In a prior art instruction prefetching device, a loss cycle is inevitable when a branch instruction appears in the instruction sequence.
An improved instruction prefetching device is disclosed in U.S. patent application Ser. No. 198,990 filed Oct. 21, 1980, by James Edward Smith. According to Unexamined Publication No. 57-76638 of the corresponding Japanese patent application filed by Control Data Corporation, the assignee of the Smith application, prefetch of the instruction sequence is carried out upon appearance of a branch instruction by predicting a branch destination or target based on prior results of execution of the branch instruction in question. When the prediction is correct, the prefetch proceeds without the loss cycle. The loss cycle, however, is three machine cycles long when the prediction fails. As will later be described herein, the loss cycle amounts to about two machine cycles long on the average.
An instruction prefetching device based on a different principle is disclosed in commonly assigned U.S. patent application Ser. No. 415,709 filed Sept. 7, 1982, now U.S. Pat. No. 4,604,691, by Masanobu Akagi, one of the present applicants. The corresponding Japanese patent application filed by NEC Corporation, the assignee, has been published as Unexamined Publication No. 57-59253. The device includes an instruction cache memory which comprises a plurality of instruction blocks for holding copies of a portion of an instruction area of a main memory. A branch information memory comprises a plurality of information blocks which correspond to the respective instruction blocks. When a branch instruction is held in one of the instruction blocks the corresponding information block is loaded with a result of any execution which has ever been carried out on the branch instruction. Another information block is loaded with an address of an instruction block. The last-mentioned instruction block holds an instruction which should very likely be prefetched next subsequent to the branch instruction. An access to the first-mentioned instruction block simultaneously to the corresponding information block is followed by an access to the other information block. An instruction sequence is prefetched at a considerably high speed. The device is, however, capable of attaining only a low accuracy of prefetch due to the prediction by block-to-block correspondence when two or more branch instructions are held in an instruction block.